Overview

Company Description:

De Beers Group is a company with a rich history and a sparkling future. Since 1888 our experts have searched the world for nature’s most precious gem. Our diamonds bring beauty to the world. But we think they can do so much more. We want our diamonds, and our business, to make life brilliant – for our people, our customers and the world around us. Venetia Mine is part of De Beers Group Managed Operations Business which integrates mines, operations and support functions in the De Beers Group producer countries of Canada and South Africa to shape a safe, sustainable future for De Beers Group’s people, shareholders, communities and partners.

Job Description:

De Beers has a dynamic portfolio of internal innovation initiatives spanning new business model, product, service and process innovations that aim to optimise the performance of the current profitable core business and simultaneously build new business. Our competitive environment demands that we operate differently, and in an integrated and connected manner, to enable faster transition of these innovation initiatives through to impact by utilizing new processes, products/services and business models. Our integrated innovation function – De Beers Group IgniteTM - has two broad deliverables:

• The identification, research, venturing, and deployment of new processes, connected technology products and services and new business models to unlock maximum value from innovation for De Beers
• Build on existing foundations to commercialise technologies to 3rd parties - growing profitable new revenue streams

These deliverables provide an emphasis on integration and delivery of connected technologies to optimize the existing core business whilst advancing our continued exploration of new business models that unlock maximum value for the De Beers Group, while also establishing and pursuing a pathway to profitable growth and additive revenue streams.

The main purpose of this role is to provide functional, performance and reliability test expertise to different development streams within the De Beers development team. This will be a hands-on role and will consist of developing, conducting and documenting test cases on a variety of De Beers products, in accordance with De Beers Group Technology standards and procedures.

• Adhere to relevant safety and environmental standards and protocols – ensure tests are carried out in accordance with safety standards and in a safe working environment.
• Conduct thorough testing of automated diamond sorting machines and instruments
• Setup and operate testing equipment - simulate real-world conditions and evaluate machine performance and reliability.
• Perform functional, performance and reliability testing – evaluate the performance of sorting machines to identify areas for improvement and bugs in hardware.
• product management, to understand machine specification, features, and requirements.
• Provide feedback and suggestions for product improvements - based on test results and observations made during the testing cycle, suggest, document and communicate to the product team potential areas of improvement. Raise and manage bugs noted during the machine testing process.
• Undertake machine setup and maintenance – prepare equipment and machines for testing including changing components where required to compare performance and functionality. Ensure machines and equipment are kept in good working order and perform relevant operator maintenance.
• Practices and demonstrates the departments ways of working, values and core beliefs – consistently displays De Beers values and ways of working whilst collaborating with other team members and the wider engineering group.

Qualifications:

• Collaborative team-player with excellent verbal and written communication skills
• Passionate about problem solving and making data led decisions
• Desirable to have experience working with electro-mechanical systems such as CNC and/or automation. Laser experience is beneficial
• Advanced Excel skills utilised to analyse data, direct further experimental test suites, and communicate findings
• Experience in designing and running experiments to validate key hypotheses
• Strong analytical skills with ability to capture, analyse, and understand data generated through experiments
• Ability to identify and resolve problems in a timely manner
• Experience of working in agile environment
• Believes in continuous learning and staying abreast of latest technologies
• Preferable to have minimum BSc in mechanical, or applicable engineering disciplines

Additional information:

• A great working environment
• Fantastic pension scheme
• 27 days of holiday + bank holidays with the opportunity to buy or sell 5 more days
• Private Healthcare
• Mental health is a top priority for De Beers Group - we offer free subscription to Headspace and have mental health first aider
• Competitive salary
• Your Choice membership discounts
• Employee share schemes 
• Staff discount
• Flexible benefits package 
• Free breakfast & lunch at onsite restaurant
• Free gym onsite

Senior Digital Design Engineer

Cambridge, Cambridgeshire

About the Role

As a Senior Digital Design Engineer you will be working to implement high performance AI inference solutions on FPGA. You will contribute to our IP library in SystemVerilog and build out complete FPGA design solutions for customers. You will work as part of our diverse team of developers and researchers, on IP that is core to our inference products. You will use your experience to deliver highly performant, well tested and extensible code for some of the most widely deployed AI in modern data centers. You will work closely with our software and machine learning engineers, integrating against Myrtle’s compiler/runtime/driver stack, to build high-reliability, low-latency, and high-throughput inference applications.
You will work with the latest AI capable FPGAs from multiple FPGA vendors to develop RTL in SystemVerilog. You will generate maintainable and parameterizable IP components, to enable reuse across multiple FPGAs and applications. You will package IP into full solution implementations, achieve timing closure through floorplanning and test solutions on the board. You will make low level software interface code changes to support integration with our software stacks. You will work in a Linux development environment.
You will help to define the ways of working in the FPGA team, including coding standards and test. You will help the team to plan activities using Agile scrum methodology.

What we do

Myrtle.ai does the engineering to make deep learning a low power, high performance reality today. Focusing on reducing the power consumption of the world’s data centers, we strive to use our expertise to transform the world today by making tomorrow’s AI inference workloads run with unsurpassed efficiency. We’re a team of engineers and scientists with deep technical expertise who love a technical challenge in a friendly collaborative environment. We focus on end to end problem optimisation, starting at the algorithm and adapting the whole stack to get world leading performance from today’s silicon solutions.

Culture

We are a small friendly team, who work with some of the biggest problems in ML today. We strive for excellent technical performance in an environment where everyone contributes directly to the company’s success. We are collaborative and multi-disciplined, welcoming innovation and critical thinking from everyone.
We are based in central Cambridge UK, and enjoy sharing food and games. We are currently running a hybrid working scheme with minimum 3 days on site, allowing a degree of home working. We can accommodate other non standard working patterns for staff with particular requirements.
Myrtle is an equal opportunity employer. We value diversity at our company and are committed to creating an inclusive environment for all employees, providing equal opportunities to all persons without discrimination. We recognize the excellent benefits in having a diverse workforce from different backgrounds and employ solely on ability.

What you will be doing

• Writing and testing IP components in SystemVerilog for FPGA
• Building full applications for FPGA using our IP library
• Integrating with third party IP for external memory PCIe subsystems
• Extending IP verification code and integrating into automated test environments
• Working with software interface routines to support FPGA integration into the software stacks
• Learning about a range of Machine Learning inference optimization techniques
• Providing technical support for customer engagements

We're excited if you have

• At least 5 years’ experience generating clear, well-documented, and well-tested SystemVerilog, Verilog or VHDL code
• Masters degree in Engineering, Mathematics or other Scientific Discipline
• Worked with FPGA EDA tools such as Quartus or Vivado
• Worked with software languages such as C, C++, Python
• Familiarity with Linux development environments, version control and CI systems
• Experience of bringing up full FPGA designs and debugging on hardware
• Experience optimising RTL designs to achieve timing closure
• Good verbal and written communication skills
• [Nice to have] Familiarity with neural network architectures
• [Nice to have] Interest in Functional Programming Languages